APS Meeting March 2006 M.Alexander
5
DDC-8
Developed by Wojtek Skulski.

Diagnostic OUT
40 MHz * 10 bits
JTAG connector
FPGA
ADC 40 MHz * 10 bits    (8 channels)
16 bidirectional TTL lines + 1 in
(pool of extra logic I/O)
Analog
signal  IN
8 channels (only 1 used)
with
digital offset
and gain control
RS-232
Logic connectors NIM 
16 lines IN, 8 lines OUT
USB 
RAM
500 kB
ECL clock IN
(optional)
micro
processor