Time-of-flight timing

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1. Timing before ADC and TDCs

The time at which the signals arrive at the ADCs and TDCs is effected by the time-of-flight of the particles to the scintillators, the propagation time in the scintillators, the transit time in the pmt, the cable length between the pmt and the discriminators, the internal delay inside the discriminators and the cable length between discriminators and ADCs and TDCs. The various times are listed in the following table.

Note: we have assumed that a CAMAC crate with the discriminators is located at the location of each section of the time-of-flight wall.

Location	T min	Tmax	Comments
BC 404	5.7	39.0	Time-of-flight for the fastest (slowest) particle detected at the minimum (maximum) distance.
PMT Output	18.4	51.7	Transit time is 8.5 ns
Disc. In	26.3	59.6	Assume 2 m of cable between pmt and discriminator.
Disc. Out	34.3	67.6	Time between input and output is 8 ns.
ADC and TDC	194.3	227.6	Assume a 160 ns delay cable.

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2. Timing of TOF trigger.

In principle, the time-of-flight wall can be triggered on it self (e.g. TDCs are started with a signal from the first scintillator). The time required to generate such a trigger is summarized in the table below.

Note: the trigger logic is located in a crate mounted below one of the sections of the time-of-flight wall. The time required for logic signals to travel from the discriminators of the various sections of the time-of-flight wall to this logic crate dominates the time required to generate this TOF trigger. We have assumed that the TOF trigger crate is located at the section of the time-of-flight wall which covers the angular range between 30 and 50 degrees.

Location	T min	Tmax	Comments
Disc. Logic	34.3	67.6	Multiplicity signals are generated by each discriminator.
Discriminator on multiplicity.	42.3	75.6	Time between input and output is 8 ns.
Arrival at TOF Trigger Crate.	85.6	118.9	Assume 11 m of cable between discriminator and TOF trigger crate (make all cables the same length).
Coincidence unit	95.6	128.9	Time between input and output is 10 ns.
Gates arrive at ADC and TDC	185.6	218.9	Cable between logic crate and ADCs and TDCs must be less than 90 ns long to ensure that the gate and start signals arrive at least 10 ns before the real signals.

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3. Conversion and read out.

1881M ADC conversion time:

• 12 microseconds for 13 bits
• 9 microseconds for 12 bits
• fast clear: 1 microseconds

   

1875A TDC conversion time:

• 10 microseconds + 2.5 microseconds per hit channel.
• Assuming an average occupancy of 15%, we expect 10 channels per module to be hit, which requires a 35 microsecond conversion time.
• fast clear: 950 ns

   

FASTBUS readout

• Rate is 165 ns per word.
• 15% occupancy of
• Assuming 4 section of the time-of-flight wall with a total of 960 channels. we require 144 words (one word per channel) to be read out.
• FASTBUS readout takes 24 microseconds for average events and 158 microseconds for 100% occupancy events.

Conclusion

• Average time for ADC/TDC readout to complete (15% occupancy): 59 microseconds.
• Maximum time for ADC/TDC readout to complete (100% occupancy): 328 microseconds.